COOLJAPAN OÜ / OxiEDA
OxiEDA — RTL to GDSII

The whole flow. One language.

Parsing, synthesis, technology mapping, floorplanning, placement, clock tree, routing, layout and sign-off — one workspace, one type system, one build. No C++ tool boundary anywhere in the chain.

20+ crates Zero C/C++ FFI Verilog / SystemVerilog LEF · DEF · Liberty GDSII · OASIS
Toolchain closure auditoxieda · full flow
LanguageToolsStatus
C0Absent
C++0Absent
Tcl0Absent
Binary blobs0Absent
unsafe Rust0Forbidden
Rust crates0All of it
Existing open flows are assembled from separate C and C++ programs glued with Tcl and file formats. Every handoff is a parser, a version skew and a place for silent data loss. This one is a library, and the netlist never leaves memory unless you ask it to. One binary
StageSequence

Eleven stages. Same address space.

The order is the flow, so it is numbered. Each stage is a crate you can call directly, or drive as a whole from one entry point.

01HDL parseoxieda-hdl-parser — Verilog, SystemVerilog
02Elaborate to IRoxieda-synth-ir — OXIL intermediate representation
03Synthesis passesoxieda-synth-passes — hierarchy, proc, opt, FSM, flatten
04Logic optimisationoxieda-abc — AIG rewriting and balancing
05Technology mappingoxieda-techmap · oxieda-liberty — cell library binding
06Floorplanoxieda-floorplan · oxieda-lef-def
07Placementoxieda-placement — global and detailed
08Clock tree synthesisoxieda-cts — skew and insertion delay
09Routingoxieda-route-global · oxieda-route-detail
10Layoutoxieda-layout — layout database and DRC hooks
11Stream outoxieda-gdsii · oxieda-oasis — tape-out formats
Clause 01Landscape

Three commercial vendors, or a pile of C++.

If you cannot pay seven figures for a seat, the open flow is your only option — and the open flow is six unrelated C and C++ programs that happen to read each other's files.

FlowCompositionLanguageIntegrationAccess
Synopsys · Cadence · SiemensComplete, qualifiedC++Vendor integratedSeat licence, export controlled
Yosys + OpenROADAssembled per projectC++Tcl and file handoffOpen source
Magic · KLayout · OpenSTAPoint toolsC / C++ManualOpen source
OxiEDASingle workspaceRustIn-process, typedLicensed, non-US entity

The interesting difference is not speed. It is that a netlist stays a typed value from elaboration through stream-out, instead of being serialised and re-parsed nine times. Errors that currently surface at DRC surface at compile time.

Clause 02Status

What is done, and what is not.

Nobody should evaluate an EDA flow on a marketing page. Here is the state of it, stated plainly, so you can decide whether the conversation is worth your time.

Verilog / SystemVerilog front end and OXIL elaborationImplemented
Synthesis passes and AIG-based logic optimisationImplemented
Liberty, LEF, DEF, GDSII and OASIS format supportImplemented
Placement, clock tree synthesis, global and detailed routingImplemented
End-to-end flow on an open PDK, GDSII compared against a reference flowIn progress
Static timing sign-off correlation against a commercial signoff toolIn progress
Silicon-proven tape-outNot yet
Advanced node support and foundry-qualified decksNot yet

If you need a qualified flow for production silicon this quarter, buy a commercial seat — we will tell you that on the call. If you are building a sovereign toolchain, a research flow, an educational programme, or a RISC-V product where the licence cost is the blocker, this is worth an hour.

Clause 03Jurisdiction

Where a toolchain is domiciled is now a design constraint.

Ownership
  • Held by COOLJAPAN OÜ, an Estonian company
  • Single copyright holder, no contributor licence chain to untangle
  • No US person in the ownership structure
  • Exclusive rights within a territory or vertical can be transferred
Supply chain
  • Every dependency built from source
  • No binary blob, no vendor runtime, no phone-home licence server
  • Reproducible builds, full SBOM per release
  • Runs air-gapped as a single static binary
Programme fit
  • National semiconductor initiatives
  • University and research flows without seat budgets
  • RISC-V and chiplet vendors
  • Defence and space where tool provenance is auditable
Clause 04Provenance

Nine years removing C. The flow is what got built on top.

Placement is optimisation. Routing is graph search on a numerical grid. Timing is sparse linear algebra. Every one of those sits on BLAS, on LAPACK, on FFT — and in every existing EDA tool, all of that is C or Fortran underneath, wrapped in C++.

So the toolchain could not be written until the numerics were replaced. We started at the bottom in 2017 and worked up. OxiEDA is not a rewrite of an EDA tool. It is the first thing that became possible once the floor underneath it was Rust.

OxiEDA RTL → GDSII └─ OptiRS placement, legalisation, optimisation └─ SciRS2 numerical core, sparse solvers └─ OxiBLAS · OxiFFT linear algebra, transforms └─ Rust standard library. Nothing further down.

A Rust EDA tool linked against a C solver still has C in the audit, and still has the FFI boundary in the review. Ours does not, because the layer beneath it was rewritten first, and the layer beneath that one before it.

Most of the stack is public on GitHub under Apache-2.0. The flow is the part we licence.

Clause 05Next

Three ways in.

Evaluation

Source access for research and academic use. Tell us the PDK and the design; you get the flow and the honest limitations.

Commercial licence

Source or integration licence for a product line. Priced per year, no royalty on your silicon, no audit clause.

Programme partnership

National or institutional toolchain work, including exclusive rights within a territory. This is the one that needs a conversation.